A hardware framework for on-chip FPGA acceleration.

Andrea Lomuscio Gian Carlo Cardarilli Alberto Nannarelli Marco Re

Published in: ISIC (2016)

Keyphrases

low cost
high speed
single chip
programmable logic
hardware implementation
field programmable gate array
hardware architectures
evolvable hardware
hardware architecture
real time
data acquisition
image processing
hardware design
computing systems
vlsi implementation
hardware and software
parallel hardware