A RISC-V Hardware Accelerator for Q-Learning Algorithm.
Damiano AngeloniLorenzo CaneseGian Carlo CardarilliLuca Di NunzioMarco ReSergio SpanòPublished in: ApplePies (2023)
Keyphrases
- learning algorithm
- hardware architecture
- field programmable gate array
- low power consumption
- low cost
- instruction set
- hardware implementation
- application specific
- machine learning algorithms
- hardware and software
- real time
- reinforcement learning
- embedded systems
- active learning
- parallel computing
- image processing algorithms
- training data
- machine learning
- learning process
- learning scheme
- learning tasks
- parallel implementation
- computing systems
- learning rate
- massively parallel
- data acquisition
- learning models
- back propagation
- high end
- computing power
- low power
- parallel hardware
- generalization ability
- classification algorithm
- training samples
- computer systems
- support vector
- image processing
- neural network