Sarma B. K. Vrudhula

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 63

Top Venues

CoRR

ISCAS

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ICCAD

Publications

Gian Singh, Sarma B. K. Vrudhula
A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. ACM Great Lakes Symposium on VLSI (2024)
Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. MLSys (2024)
Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA (2024)
Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (3) (2024)
Gyudong Kim, Mehdi Ghasemi, Soroush Heidari, Seungryong Kim, Young Geun Kim, Sarma B. K. Vrudhula, Carole-Jean Wu
HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated Learning. CoRR (2024)
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. ISQED (2023)
Gian Singh, Sanmukh R. Kuppannagari, Sarma B. K. Vrudhula
PARAG: PIM Architecture for Real-Time Acceleration of GCNs. HiPC (2023)
Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells. CoRR (2022)
Mehdi Ghasemi, Daler N. Rakhmatov, Carole-Jean Wu, Sarma B. K. Vrudhula
EdgeWise: Energy-efficient CNN Computation on Edge Devices under Stochastic Communication Delays. ACM Trans. Embed. Comput. Syst. 21 (5) (2022)
Kyler R. Scott, Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula
A Flash-based Current-mode IC to Realize Quantized Neural Networks. DATE (2022)
Ayushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. ICCAD (2022)
Ankit Wagle, Sarma B. K. Vrudhula
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Soroush Heidari, Mehdi Ghasemi, Young Geun Kim, Carole-Jean Wu, Sarma B. K. Vrudhula
CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs. IEEE Trans. Computers 71 (12) (2022)
Mehdi Ghasemi, Soroush Heidari, Young Geun Kim, Aaron Lamb, Carole-Jean Wu, Sarma B. K. Vrudhula
Energy-Efficient Mapping for a Network of DNN Models at the Edge. SMARTCOMP (2021)
Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. CoRR (2021)
Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
CIDAN: Computing in DRAM with Artificial Neurons. ICCD (2021)
Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri
CIDAN: Computing in DRAM with Artificial Neurons. CoRR (2021)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo
Performance Modeling for CNN Inference Accelerators on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Mohammad Farhadi, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang
Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CVPR Workshops (2020)
Elham Azari, Sarma B. K. Vrudhula
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. ACM Trans. Embed. Comput. Syst. 19 (1) (2020)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-Sun Seo
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Elham Azari, Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. ISQED (2020)
Ankit Wagle, Sunil P. Khatri, Sarma B. K. Vrudhula
A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. ICCD (2020)
Mohammad Farhadi Bajestani, Mehdi Ghasemi, Sarma B. K. Vrudhula, Yezhou Yang
Enabling Incremental Knowledge Transfer for Object Detection at the Edge. CoRR (2020)
Elham Azari, Sarma B. K. Vrudhula
An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing. IEEE BigData (2019)
Ankit Wagle, Elham Azari, Sarma B. K. Vrudhula
Embedding Binary Perceptrons in FPGA to improve Area, Power and Performance. ICCAD (2019)
Elham Azari, Sarma B. K. Vrudhula
ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained Devices. CoRR (2019)
Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties. IEEE Trans. Mob. Comput. 18 (12) (2019)
Elham Azari, Aykut Dengi, Sarma B. K. Vrudhula
An Energy-Efficient FPGA Implementation of an LSTM Network Using Approximate Computing. FPGA (2019)
Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
Threshold Logic in a Flash. ICCD (2019)
Ankit Wagle, Gian Singh, Jinghua Yang, Sunil P. Khatri, Sarma B. K. Vrudhula
Threshold Logic in a Flash. CoRR (2019)
Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Davesh Shingari, Akhil Arunkumar, Benjamin Gaudette, Sarma B. K. Vrudhula, Carole-Jean Wu
DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference. ISPASS (2018)
Ankit Wagle, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power and Area. FPL (2018)
Yufei Ma, Tu Zheng, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs. ICCAD (2018)
Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62 (2018)
Yufei Ma, Minkyu Kim, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
End-to-end scalable FPGA accelerator for deep residual networks. ISCAS (2017)
Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. DAC (2017)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA (2017)
Mehmet Ince, Sule Ozev, Sarma B. K. Vrudhula
Statistical library characterization using arbitrary polynomial chaos. LASCAS (2017)
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. FPL (2017)
Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24 (9) (2016)
Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL (2016)
Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
Improving smartphone user experience by balancing performance and energy with probabilistic QoS guarantee. HPCA (2016)
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA (2016)
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
Digital IP protection using threshold voltage control. ISQED (2016)
Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
High-performance face detection with CPU-FPGA acceleration. ISCAS (2016)
Niranjan Kulkarni, Sarma B. K. Vrudhula
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. CoRR (2016)
Debayan Mahalanabis, M. Sivaraj, W. Chen, S. Shah, Hugh J. Barnaby, Michael N. Kozicki, Jennifer Blain Christen, Sarma B. K. Vrudhula
Demonstration of spike timing dependent plasticity in CBRAM devices with silicon neurons. ISCAS (2016)
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
Digital IP Protection Using Threshold Voltage Control. CoRR (2016)
Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang
Design of threshold logic gates using emerging devices. ISCAS (2015)
Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems 39 (8) (2015)
Yufei Ma, Minkyu Kim, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits. ICCD (2015)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Debayan Mahalanabis, Vineeth Bharadwaj, Hugh J. Barnaby, Sarma B. K. Vrudhula, Michael N. Kozicki
A Nonvolatile Sense Amplifier Flip-Flop Using Programmable Metallization Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC (2015)
Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula
Fast and robust differential flipflops and their extension to multi-input threshold gates. ISCAS (2015)
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD (2015)
Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE (2015)
Vinay Hanumaiah, Digant Desai, Benjamin Gaudette, Carole-Jean Wu, Sarma B. K. Vrudhula
STEAM: A Smart Temperature and Energy Aware Multicore Controller. ACM Trans. Embed. Comput. Syst. 13 (5s) (2014)
Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
Branch-Aware Loop Mapping on CGRAs. DAC (2014)
Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH (2014)
Vinay Hanumaiah, Sarma B. K. Vrudhula
Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling. IEEE Trans. Computers 63 (2) (2014)
Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS (2014)
Zihan Xu, Matteo Cavaliere, Pei An, Sarma B. K. Vrudhula, Yu Cao
The Stochastic Loss of Spikes in Spiking Neural P Systems: Design and Implementation of Reliable Arithmetic Circuits. Fundam. Informaticae 134 (1-2) (2014)
Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula
A fast, energy efficient, field programmable threshold-logic array. FPT (2014)
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. J. Parallel Distributed Comput. 74 (6) (2014)
Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA (2014)
Benjamin Gaudette, Vinay Hanumaiah, Marwan Krunz, Sarma B. K. Vrudhula
Maximizing Quality of Coverage under Connectivity Constraints in Solar-Powered Active Wireless Sensor Networks. ACM Trans. Sens. Networks 10 (4) (2014)
Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs). DAC (2013)
Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula
EPIMap: using epimorphism to map applications on CGRAs. DAC (2012)
Benjamin Gaudette, Vinay Hanumaiah, Sarma B. K. Vrudhula, Marwan Krunz
Optimal range assignment in solar powered active wireless sensor networks. INFOCOM (2012)
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. NANOARCH (2012)
Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula
Minimizing area and power of sequential CMOS circuits using threshold decomposition. ICCAD (2012)
Vinay Hanumaiah, Sarma B. K. Vrudhula
Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors. IEEE Trans. Computers 61 (10) (2012)
Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
Temperature dependent wire delay estimation in floorplanning. NORCHIP (2011)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski
Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula
-1} and its reverse converter design for efficient fir filter implementation. ACM Great Lakes Symposium on VLSI (2011)
Vinay Hanumaiah, Sarma B. K. Vrudhula
Reliability-aware thermal management for hard real-time applications on multi-core processors. DATE (2011)
Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula
Enabling Multithreading on CGRAs. ICPP (2011)
Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI (2010)
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang, Sarma B. K. Vrudhula
Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Performance optimal speed control of multi-core processors under thermal constraints. DATE (2009)
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
Throughput optimal task allocation under thermal constraints for multi-core processors. DAC (2009)
Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS (2009)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD (2009)
Ravishankar Rao, Sarma B. K. Vrudhula
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (10) (2009)
Amit Goel, Sarma B. K. Vrudhula
Current source based standard cell model for accurate signal integrity and timing analysis. DATE (2008)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. 2 (4) (2008)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electron. 4 (1) (2008)
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design (2008)
Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski
Analytical results for design space exploration of multi-core processors employing thread migration. ISLPED (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Sarma B. K. Vrudhula