Sarvesh Bhardwaj

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 1

Top Topics

Branch And Bound Algorithm

Lower And Upper Bounds

Integer Programming

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ankur Sharma, David G. Chinnery, Tiago Reimann, Sarvesh Bhardwaj, Chris Chu
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Ankur Sharma, David G. Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu
Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading. ICCAD (2015)
Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe
On Timing Closure: Buffer Insertion for Hold-Violation Removal. DAC (2014)
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Satyajayant Misra, Guoliang Xue, Sarvesh Bhardwaj
Secure and Robust Localization in a Wireless Ad Hoc Environment. IEEE Trans. Veh. Technol. 58 (3) (2009)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (3) (2008)
Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
Scalable model for predicting the effect of negative bias temperature instability for reliable design. IET Circuits Devices Syst. 2 (4) (2008)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. J. Low Power Electron. 4 (1) (2008)
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Power Reduction of Functional Units Considering Temperature and Process Variations. VLSI Design (2008)
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Temperature and Process Variations Aware Power Gating of Functional Units. VLSI Design (2008)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (10) (2008)
Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. PATMOS (2007)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. VLSI Design (2007)
Sarma B. K. Vrudhula, Sarvesh Bhardwaj
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. VLSI Design (2007)
Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao
The Impact of NBTI on the Performance of Combinational and Sequential Circuits. DAC (2007)
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
Stochastic variational analysis of large power grids considering intra-die correlations. DAC (2006)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. DAC (2006)
Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. ASP-DAC (2006)
Sarvesh Bhardwaj, Wenping Wang, Rakesh Vattikonda, Yu Cao, Sarma B. K. Vrudhula
Predictive Modeling of the NBTI Effect for Reliable Design. CICC (2006)
Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula
A framework for statistical timing analysis using non-linear delay and slew models. ICCAD (2006)
Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. J. Low Power Electron. 2 (2) (2006)
Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. ISQED (2006)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. DAC (2005)
Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang
An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC (2005)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. ICCAD (2005)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design (2004)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
AU: Timing Analysis Under Uncertainty. ICCAD (2003)
Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David T. Blaauw
Estimation of signal arrival times in the presence of delay noise. ICCAD (2002)