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An efficient combinationality check technique for the synthesis of cyclic combinational circuits.

Vineet AgarwalNavneeth KankaniRavishankar RaoSarvesh BhardwajJanet Meiling Wang
Published in: ASP-DAC (2005)
Keyphrases
  • logic synthesis
  • analog circuits
  • asynchronous circuits
  • logic circuits
  • high speed
  • delay insensitive
  • databases
  • computationally efficient
  • database
  • image processing
  • database systems
  • texture synthesis