Karam S. Chatha

Publication Activity (10 Years)

Years Active: 1998-2014
Publications (10 Years): 0

Top Topics

Stream Processing

Complex Event Processing

Multicore Processors

Dynamic Scheduling

Top Venues

ACM Trans. Embed. Comput. Syst.

IEEE Embed. Syst. Lett.

Publications

Ran Ginosar, Karam S. Chatha
Guest Editors' Introduction - Special Issue on Network-on-Chip. IEEE Trans. Computers 63 (3) (2014)
Amrit Panda, Karam S. Chatha
An Embedded Architecture for Energy-Efficient Stream Computing. IEEE Embed. Syst. Lett. 6 (3) (2014)
Amrit Panda, Karam S. Chatha
An embedded co-processor architecture for energy-efficient stream computing. ESTIMedia (2014)
Weijia Che, Karam S. Chatha
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors. ACM Trans. Embed. Comput. Syst. 13 (1s) (2013)
Weijia Che, Karam S. Chatha
Unrolling and retiming of stream applications onto embedded multicore processors. DAC (2012)
Haeseung Lee, Weijia Che, Karam S. Chatha
Dynamic scheduling of stream programs on embedded multi-core processors. CODES+ISSS (2012)
Glenn Leary, Weijia Che, Karam S. Chatha
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. DAC (2012)
Weijia Che, Karam S. Chatha
Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming. DAC (2011)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (11) (2011)
Weijia Che, Karam S. Chatha
Scheduling of stream programs onto SPM enhanced processors with code overlay. ESTIMedia (2011)
Glenn Leary, Karam S. Chatha
A holistic approach to network-on-chip synthesis. CODES+ISSS (2010)
Weijia Che, Karam S. Chatha
Scheduling of synchronous data flow models on scratchpad memory based embedded processors. ICCAD (2010)
Glenn Leary, Karam S. Chatha
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. VLSI Design (2010)
Sushu Zhang, Karam S. Chatha
Thermal aware task sequencing on embedded processors. DAC (2010)
Weijia Che, Karam S. Chatha
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine. ASAP (2010)
Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha
A performance model and code overlay generator for scratchpad enhanced embedded processors. CODES+ISSS (2010)
Weijia Che, Amrit Panda, Karam S. Chatha
Compilation of stream programs for multicore processors that incorporate scratchpad memories. DATE (2010)
Michael A. Baker, Karam S. Chatha
A lightweight run-time scheduler for multitasking multicore stream applications. ICCD (2010)
Saraju P. Mohanty, Nasir D. Memon, Karam S. Chatha
Circuits and systems for real-time security and copyright protection of multimedia. Comput. Electr. Eng. 35 (2) (2009)
Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Performance optimal speed control of multi-core processors under thermal constraints. DATE (2009)
Sushu Zhang, Karam S. Chatha, Goran Konjevod
Near optimal battery-aware energy management. ISLPED (2009)
Glenn Leary, Karam S. Chatha
Automated technique for design of NoC with minimal communication latency. CODES+ISSS (2009)
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
Throughput optimal task allocation under thermal constraints for multi-core processors. DAC (2009)
Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS (2009)
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD (2009)
Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li
Power reduction via macroblock prioritization for power aware H.264 video applications. CODES+ISSS (2008)
Sushu Zhang, Karam S. Chatha
System-level thermal aware design of applications with uncertain execution time. ICCAD (2008)
Sushu Zhang, Karam S. Chatha
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. ASP-DAC (2008)
Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ASP-DAC (2007)
Christopher Ostler, Karam S. Chatha, Goran Konjevod
Approximation Algorithm for Process Mapping on Network Processor Architectures. ASP-DAC (2007)
Krishnan Srinivasan, Karam S. Chatha
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. Integr. 40 (3) (2007)
Sushu Zhang, Karam S. Chatha, Goran Konjevod
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. ISLPED (2007)
Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan
ILP and heuristic techniques for system-level design on network processor architectures. ACM Trans. Design Autom. Electr. Syst. 12 (4) (2007)
Christopher Ostler, Karam S. Chatha
An ILP formulation for system-level application mapping on network processor architectures. DATE (2007)
Michael A. Baker, Aviral Shrivastava, Karam S. Chatha
Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS (2007)
Sushu Zhang, Karam S. Chatha
Approximation algorithm for the temperature-aware scheduling problem. ICCAD (2007)
Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu
Optimization of media processing workflows with adaptive operator behaviors. Multim. Tools Appl. 33 (3) (2007)
Glenn Leary, Krishna Mehta, Karam S. Chatha
Performance and resource optimization of NoC router architecture for master and slave IP cores. CODES+ISSS (2007)
Christopher Ostler, Karam S. Chatha
Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. DAC (2007)
Krishnan Srinivasan, Karam S. Chatha
A low complexity heuristic for design of custom network-on-chip architectures. DATE (2006)
Krishnan Srinivasan, Karam S. Chatha
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. ISQED (2006)
Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino
Modular Design of Media Retrieval Workflows Using ARIA. CIVR (2006)
Krishnan Srinivasan, Karam S. Chatha
Layout aware design of mesh based NoC architectures. CODES+ISSS (2006)
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. Syst. 14 (4) (2006)
Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integr. 38 (3) (2005)
Krishnan Srinivasan, Karam S. Chatha
SAGA: synthesis technique for guaranteed throughput NoC architectures. ASP-DAC (2005)
Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen
Media processing workflow design and execution with ARIA. ACM Multimedia (2005)
Krishnan Srinivasan, Karam S. Chatha
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. VLSI Design (2005)
Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. ISVLSI (2005)
Nagendran Rangan, Karam S. Chatha
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. VLSI Design (2005)
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
An automated technique for topology and route generation of application specific on-chip interconnection networks. ICCAD (2005)
Krishnan Srinivasan, Karam S. Chatha
A technique for low energy mapping and routing in network-on-chip architectures. ISLPED (2005)
Krishnan Srinivasan, Karam S. Chatha
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. VLSI Design (2004)
Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. ISVLSI (2004)
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. ICCD (2004)
Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. ISVLSI (2004)
Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha
A Power and Performance Model for Network-on-Chip Architectures. DATE (2004)
K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer
Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. Multimedia Information Systems (2004)
Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
Quality-of-service and error control techniques for network-on-chip architectures. ACM Great Lakes Symposium on VLSI (2004)
Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram
ARIA: an adaptive and programmable media-flow architecture for interactive arts. ACM Multimedia (2004)
Karam S. Chatha, Ranga Vemuri
Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Karam S. Chatha, Ranga Vemuri
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES (2001)
Karam S. Chatha, Ranga Vemuri
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. Des. Autom. Embed. Syst. 5 (3-4) (2000)
Karam S. Chatha, Ranga Vemuri
Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL (1999)
Karam S. Chatha, Ranga Vemuri
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping (1999)
Karam S. Chatha, Ranga Vemuri
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping (1998)
Karam S. Chatha, Ranga Vemuri
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS (1998)
Karam S. Chatha, Ranga Vemuri
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES (1998)