A technique for low energy mapping and routing in network-on-chip architectures.
Krishnan SrinivasanKaram S. ChathaPublished in: ISLPED (2005)
Keyphrases
- low energy
- network on chip
- routing algorithm
- interconnection networks
- cluster head
- electron microscopy
- wireless sensor networks
- shortest path
- ad hoc networks
- routing protocol
- multipath
- fault tolerant
- parallel algorithm
- routing problem
- network traffic
- message passing
- protein folding
- end to end delay
- energy consumption
- network simulator
- multistage
- multi hop
- multi processor
- real time
- mobile ad hoc networks
- low cost
- energy efficient
- sensor nodes