A scalable parallel H.264 decoder on the cell broadband engine architecture.
Michael A. BakerPravin DalaleKaram S. ChathaSarma B. K. VrudhulaPublished in: CODES+ISSS (2009)
Keyphrases
- multi processor
- master slave
- fpga implementation
- distributed processing
- parallel architecture
- multiprocessor architecture
- shared memory
- parallel implementation
- real time
- parallel processing
- processing units
- processing elements
- low complexity
- hardware implementation
- management system
- scalable distributed
- level parallelism
- processor array
- image processing algorithms
- parallel computing
- platform independent
- single processor
- motion compensation
- multithreading
- multi core processors