Naveen Suda

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 24

Top Topics

Convolutional Neural Networks

Video Super Resolution

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Junxiao Shen, Matthias De Lange, Xuhai "Orson" Xu, Enmin Zhou, Ran Tan, Naveen Suda, Maciej Lazarewicz, Per Ola Kristensson, Amy Karlson, Evan Strasnick
Towards Open-World Gesture Recognition. CoRR (2024)
Kartikeya Bhardwaj, Milos Milosavljevic, Liam O'Neil, Dibakar Gope, Ramon Matas Navarro, Alex Chalfin, Naveen Suda, Lingchuan Meng, Danny Loh
Collapsible Linear Blocks for Super-Efficient Super Resolution. MLSys (2022)
Kartikeya Bhardwaj, Milos Milosavljevic, Alex Chalfin, Naveen Suda, Liam O'Neil, Dibakar Gope, Lingchuan Meng, Ramon Matas Navarro, Danny Loh
Collapsible Linear Blocks for Super-Efficient Super Resolution. CoRR (2021)
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
EdgeAl: A Vision for Deep Learning in the IoT Era. IEEE Des. Test 38 (4) (2021)
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
Dream Distillation: A Data-Independent Model Compression Framework. CoRR (2019)
Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu
EdgeAI: A Vision for Deep Learning in IoT Era. CoRR (2019)
Jeya Vikranth Jeyakumar, Liangzhen Lai, Naveen Suda, Mani B. Srivastava
SenseHAR: a robust virtual activity sensor for smartphones and wearables. SenSys (2019)
Liangzhen Lai, Naveen Suda
Enabling deep learning at the IoT edge. ICCAD (2018)
Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network. ISCA (2018)
Yue Zhao, Meng Li, Liangzhen Lai, Naveen Suda, Damon Civin, Vikas Chandra
Federated Learning with Non-IID Data. CoRR (2018)
Liangzhen Lai, Naveen Suda
Rethinking Machine Learning Development and Deployment for Edge Devices. CoRR (2018)
Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62 (2018)
Liangzhen Lai, Naveen Suda, Vikas Chandra
Not All Ops Are Created Equal! CoRR (2018)
Liangzhen Lai, Naveen Suda, Vikas Chandra
CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs. CoRR (2018)
Liangzhen Lai, Naveen Suda, Vikas Chandra
Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations. CoRR (2017)
Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Joon Kyung Kim, Vikas Chandra, Hadi Esmaeilzadeh
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks. CoRR (2017)
Yundong Zhang, Naveen Suda, Liangzhen Lai, Vikas Chandra
Hello Edge: Keyword Spotting on Microcontrollers. CoRR (2017)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS (2017)
Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control. CoRR (2017)
Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC (2017)
Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL (2016)
Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2016)
Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA (2016)
Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao
High-performance face detection with CPU-FPGA acceleration. ISCAS (2016)
Raveesh Magod, Naveen Suda, Vadim Ivanov, Ravi Balasingam, Bertan Bakkaloglu
A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference. CICC (2015)
Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)