A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits.
Niranjan KulkarniAykut DengiSarma B. K. VrudhulaPublished in: DAC (2017)
Keyphrases
- power consumption
- high speed
- circuit design
- duty cycle
- power reduction
- power dissipation
- low power
- significantly reduced
- power saving
- integrated circuit
- information gain
- hardware architecture
- digital circuits
- power management
- information systems
- optimal strategy
- vlsi circuits
- delay insensitive
- chip design
- clock gating
- real time
- selection strategy
- efficient implementation
- case study
- data sets