Niranjan Kulkarni

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 10

Top Topics

Threshold Selection

Energy Efficient

Boolean Networks

Top Venues

Publications

Ankit Wagle, Jinghua Yang, Niranjan Kulkarni, Sarma B. K. Vrudhula
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. DAC (2017)
Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 24 (9) (2016)
Sachin Mungmode, R. R. Sedamkar, Niranjan Kulkarni
An Enhanced Edge Adaptive Steganography Approach Using Threshold Value for Region Selection. CoRR (2016)
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
Digital IP protection using threshold voltage control. ISQED (2016)
Niranjan Kulkarni, Sarma B. K. Vrudhula
Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean Networks. CoRR (2016)
Joseph Davis, Niranjan Kulkarni, Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula
Digital IP Protection Using Threshold Voltage Control. CoRR (2016)
Sarma B. K. Vrudhula, Niranjan Kulkarni, Jinghua Yang
Design of threshold logic gates using emerging devices. ISCAS (2015)
Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. CICC (2015)
Jinghua Yang, Niranjan Kulkarni, Joseph Davis, Sarma B. K. Vrudhula
Fast and robust differential flipflops and their extension to multi-input threshold gates. ISCAS (2015)
Jinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula
Integration of threshold logic gates with RRAM devices for energy efficient and robust operation. NANOARCH (2014)
Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula
A fast, energy efficient, field programmable threshold-logic array. FPT (2014)
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
Spintronic Threshold Logic Array (STLA) - A compact, low leakage, non-volatile gate array architecture. J. Parallel Distributed Comput. 74 (6) (2014)
Nishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula
Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architecture. NANOARCH (2012)
Niranjan Kulkarni, Nishant Nukala, Sarma B. K. Vrudhula
Minimizing area and power of sequential CMOS circuits using threshold decomposition. ICCAD (2012)
Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski
Identification of Threshold Functions and Synthesis of Threshold Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Radim Belohlávek, Niranjan Kulkarni, Vilém Vychodil
A Novel Approach to Cell Formation. ICFCA (2009)