Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.
Yufei MaYu CaoSarma B. K. VrudhulaJae-sun SeoPublished in: FPGA (2017)
Keyphrases
- convolutional neural networks
- convolutional network
- high speed
- hardware implementation
- field programmable gate array
- data flow
- parallel computing
- control flow
- systolic array
- hardware design
- deep learning
- dedicated hardware
- dynamic reconfiguration
- real time image processing
- software implementation
- real time
- efficient implementation
- low cost