Tuo-Hung Hou

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 20

Top Topics

Practical Application

Close Proximity

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

VLSI Technology and Circuits

Publications

Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser
Roadmap to Neuromorphic Computing with Emerging Technologies. CoRR (2024)
Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang
A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. DATE (2024)
Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits (2023)
Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang
FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. ISCAS (2023)
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
I-Ting Wang, Chih-Cheng Chang, Yen-Yu Chen, Yi-Shin Su, Tuo-Hung Hou
Two-dimensional materials for artificial synapses: toward a practical application. Neuromorph. Comput. Eng. 2 (1) (2022)
Ming-Chun Hong, Yao-Jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, Sk. Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou
A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. VLSI Technology and Circuits (2022)
Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT (2022)
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
Hardware-Robust In-RRAM-Computing for Object Detection. CoRR (2022)
Fu-Xiang Liang, I-Ting Wang, Tuo-Hung Hou
Progress and Benchmark of Spiking Neuron Devices and Circuits. Adv. Intell. Syst. 3 (8) (2021)
Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC (2021)
Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE Using OxRAM Crossbar. CoRR (2020)
Chih-Pin Lin, Hao-Hua Hsu, Tuo-Hung Hou
Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering. DRC (2020)
Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri
Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. ISCAS (2020)
Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou
NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. DAC (2019)
Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices. CoRR (2018)
Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (1) (2018)
Chih-Cheng Chang, Pin-Chun Chen, Teyuh Chou, I-Ting Wang, Boris Hudec, Che-Chia Chang, Chia-Ming Tsai, Tian-Sheuan Chang, Tuo-Hung Hou
Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network based on Analog Resistive Synapse. CoRR (2017)
Boris Hudec, Chung-Wei Hsu, I-Ting Wang, Wei-Li Lai, Che-Chia Chang, Taifang Wang, Karol Fröhlich, Chia-Hua Ho, Chen-Hsi Lin, Tuo-Hung Hou
3D resistive RAM cell design for high-density storage class memory - a review. Sci. China Inf. Sci. 59 (6) (2016)
Chun-Tse Chou, Boris Hudec, Chung-Wei Hsu, Wei-Li Lai, Chih-Cheng Chang, Tuo-Hung Hou
bilayer RRAM. Microelectron. Reliab. 55 (11) (2015)
Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD (2015)
Shantanu Rajwade, Wing-Kei S. Yu, Sarah Q. Xu, Tuo-Hung Hou, G. Edward Suh, Edwin Kan
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. SoCC (2010)