Kang-Yu Chang

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 7

Top Topics

Top Venues

Publications

Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT (2022)
Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD (2022)
Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. ISCAS (2021)
Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC (2021)
Yu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang, Jia-Yin Chen, Shyh-Jye Jou
A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. VLSI-DAT (2021)
Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD (2020)
Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. ASICON (2019)
Kang-Yu Chang, Zhi-Ming Lin
Level Selection Based 4-PAM Transmitter for Chip to Chip Communication. APCCAS (2006)