A Reconfigurable In-SRAM Computing Architecture for DCNN Applications.

Yu-Hsien Lin Chi Liu Chia-Lin Hu Kang-Yu Chang Jia-Yin Chen Shyh-Jye Jou

Published in: VLSI-DAT (2021)

Keyphrases

hardware implementation
systolic array
management system
software architecture
real time
power consumption
reconfigurable architecture
network architecture
low power
low cost
data flow
architectural design
parallel architecture
dynamic reconfiguration
computation intensive
neural network
data sets