Jen-Chieh Liu

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 11

Top Topics

Alarm Correlation

Error Reduction

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Hong-Yi Huang, Jen-Chieh Liu, Fu-Chien Tsai, Kun-Hua Lee, Kun-Yuan Chen
A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique. Circuits Syst. Signal Process. 42 (4) (2023)
Jen-Chieh Liu, Yu-Ping Li
A Low Supply Voltage All-Digital Phase-Locked Loop With a Bootstrapped and Forward Interpolation Digitally Controlled Oscillator. IEEE Access 9 (2021)
Yo-Hao Tu, Kuo-Hsing Cheng, Man-Ju Lee, Jen-Chieh Liu
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Chi-Yang Chang
Low supply voltage and multiphase all-digital crystal-less clock generator. IET Circuits Devices Syst. 12 (6) (2018)
Jen-Chieh Liu, Tzu-Yun Wu, Tuo-Hung Hou
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee
A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2017)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture. IEICE Trans. Electron. (6) (2016)
Jen-Chieh Liu, Pei-Ying Lee
A Low Power Pulse Generator for Test Platform Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Yo-Hao Tu, Kuo-Hsing Cheng, Wei-Ren Wang, Jen-Chieh Liu, Hong-Yi Huang
A chaotically injected timing technique for ring-based oscillators. DDECS (2016)
Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu
A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. IEICE Electron. Express 13 (2) (2016)
Hong-Yi Huang, Jen-Chieh Liu, Pei-Ying Lee, Kun-Yuan Chen, Jin-Sheng Chen, Kuo-Hsing Cheng, Tzuen-Hsi Huang, Ching-Hsing Luo, Jin-Chern Chiou
PVT Insensitive High-Resolution Time to Digital Converter for Intraocular Pressure Sensing. DDECS (2015)
Jen-Chieh Liu, Huan-Ke Chiu, Jia-Hung Peng, Yuan-Hua Chu, Hong-Yi Huang
A radio-controlled receiver for clocks/watches and alarm applications. ISCAS (2014)
Hong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng
A 64-MHz∼640-MHz 64-phase clock generator. DDECS (2014)
Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Chih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng
Auto-calibration techniques in built-in jitter measurement circuit. DDECS (2012)
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang
A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Tzu-Chi Huang, Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng, Ching-Hsing Luo
All digital phase-locked loop using active inductor oscillator and novel locking algorithm. ISCAS (2011)
Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang, Yu-Liang Li, Yong-Jhen Jhu
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Kuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop. DDECS (2010)
Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen
A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC (2010)
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS (2009)
Hong-Yi Huang, Jen-Chieh Liu, Kuo-Hsing Cheng
All-Digital PLL Using Pulse-Based DCO. ICECS (2007)
Hong-Yi Huang, Bo-Ruei Wang, Jen-Chieh Liu
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit. ISCAS (2006)