A loading effect insensitive and high precision clock synchronization circuit.
Kai-Wei HongKuo-Hsing ChengChi-Hsiang ChenJen-Chieh LiuChien-Cheng ChenPublished in: ESSCIRC (2010)
Keyphrases
- high precision
- high recall
- high speed
- duty cycle
- high reliability
- power consumption
- high accuracy
- achieve high precision
- data sets
- circuit design
- information systems
- artificial intelligence
- real time
- control system
- search algorithm
- case study
- decision trees
- image processing
- knowledge base
- logic circuits
- power reduction
- databases
- phase locked loop