Kai-Wei Hong

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Dynamically Changing

Power Consumption

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang
An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, Jen-Chieh Liu
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Kuo-Hsing Cheng, Jen-Chieh Liu, Chih-Yu Chang, Shu-Yu Jiang, Kai-Wei Hong
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 19 (8) (2011)
Kai-Wei Hong, Kuo-Hsing Cheng, Chi-Hsiang Chen, Jen-Chieh Liu, Chien-Cheng Chen
A loading effect insensitive and high precision clock synchronization circuit. ESSCIRC (2010)
Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Trans. Electron. (7) (2009)
Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. J. Circuits Syst. Comput. 18 (5) (2009)
Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu
A low jitter self-calibration PLL for 10Gbps SoC transmission links application. ICECS (2008)
Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS (2006)