Chia-Chun Tsai

Publication Activity (10 Years)

Years Active: 1990-2022
Publications (10 Years): 8

Top Topics

Defect Detection

Hybrid Architecture

Textured Surfaces

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Adv. Eng. Informatics

Publications

Ssu-Han Chen, Yu-Wei Lai, Chung-Lun Kuo, Chieh-Yi Lo, Yu-Sung Lin, Yan-Rung Lin, Chih-Hsiang Kang, Chia-Chun Tsai
A surface defect detection system for golden diamond pineapple based on CycleGAN and YOLOv4. J. King Saud Univ. Comput. Inf. Sci. 34 (Issue) (2022)
Ssu-Han Chen, Chia-Chun Tsai
SMD LED chips defect detection using a YOLOv3-dense model. Adv. Eng. Informatics 47 (2021)
Chia-Chun Tsai, Chih-Chia Kuo, Yen-Lun Chen
. CASE (2020)
Chia-Chun Tsai
Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period. ISOCC (2019)
Chia-Chun Tsai
Embedded bus switches on 3D data bus for critical access time reduction. LASCAS (2018)
Chia-Chun Tsai
Minimizing Critical Access Time for 3D Data Bus Based on Inserted Bus Switches and Repeaters. ISVLSI (2017)
Shin-Chi Lai, Wen-Ho Juang, Yueh-Shu Lee, Shin-Hao Chen, Ke-Horng Chen, Chia-Chun Tsai, Chiung-Hon Lee
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform. IEEE Trans. Circuits Syst. II Express Briefs (3) (2016)
Hong-Tzer Yang, Chiao-Tung Yang, Chia-Chun Tsai, Guan-Jhih Chen, Szu-Yao Chen
Improved PSO based home energy management systems integrated with demand response in a smart grid. CEC (2015)
Chia-Chun Tsai
A reduced Li-Ion battery charger for portable applications. ICNC (2013)
Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, Haixia Wu
Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology. CISIS (2013)
Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. Integr. 45 (1) (2012)
Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee
Micro fuel cell power management circuit design for portable devices. FSKD (2012)
Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. J. Circuits Syst. Comput. 20 (8) (2011)
Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2011)
Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. Integr. 44 (1) (2011)
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
Antenna Violation Avoidance/Fixing for X-clock routing. ISQED (2010)
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
Double-via insertion enhanced X-architecture clock routing for reliability. ISCAS (2010)
Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. J. Inf. Sci. Eng. 26 (4) (2010)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion. Circuits Syst. Signal Process. 28 (6) (2009)
Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. J. Circuits Syst. Comput. 18 (5) (2009)
Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. J. Circuits Syst. Comput. 18 (5) (2009)
Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
X-clock routing based on pattern matching. SoCC (2008)
Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee
Layer assignment considering manufacturability in X-architecture clock tree. CIT (2008)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. IMECS (2007)
Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2007)
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. IIH-MSP (2007)
Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao
A single chip image sensor embedded smooth spatial filter with A/D conversion. ISCAS (2006)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS (2006)
Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22 (6) (2006)
Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao
Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS (2006)
Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS (2006)
Chun-Ying Lai, Shyh-Kang Jeng, Yao-Wen Chang, Chia-Chun Tsai
Inductance extraction for general interconnect structures. ISCAS (2006)
Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. ICICIC (2) (2006)
Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
A new low-power turbo decoder using HDA-DHDD stopping iteration. ISCAS (2) (2005)
Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee
Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) (2005)
Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
A new CCII-based pipelined analog to digital converter. ISCAS (6) (2005)
Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang
RCGES: Retargetable Code Generation for Embedded Systems. ATVA (2004)
Pei-Yung Hsiao, Yu-Chun Hsu, Wen-Ta Lee, Chia-Chun Tsai, Chia-Hao Lee
An embedded analog spatial filter design of the current-mode CMOS image sensor. IEEE Trans. Consumer Electron. 50 (3) (2004)
Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai
Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
An Automatic Router for the Pin Grid Array Package. ASP-DAC (1999)
Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC (1999)
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD (1999)
Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen
NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (2) (1998)
Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen
Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2 (2) (1997)
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng
Performance driven bus buffer insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (4) (1996)
Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin
Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC (1995)
Chia-Chun Tsai, Sao-Jie Chen
A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10 (1) (1994)
Pei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai
Minimum Partition for the Space Region of VLSI Layout. VLSI Design (1992)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (8) (1992)
Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng
A knowledge-based program for compacting mask layout of integrated circuits. Comput. Aided Des. 23 (3) (1991)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22 (7) (1990)
Pei-Yung Hsiao, Chia-Chun Tsai
A new plane-sweep algorithm based on spatial data structure for overlapped rectangles in 2-D plane. COMPSAC (1990)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
Tile-Expansion Router. J. Inf. Sci. Eng. 6 (3) (1990)