Wu-Shiung Feng

Publication Activity (10 Years)

Years Active: 1988-2017
Publications (10 Years): 2

Top Topics

Probability Distribution

Top Venues

Publications

Hwang-Cherng Chow, Prasenjit Chatterjee, Wu-Shiung Feng
A Simple Drain Current Model for MOS Transistors with the Lorentz Force Effect. Sensors 17 (6) (2017)
Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng
Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application. Sensors 16 (9) (2016)
Chen-Yuan Chu, Chien-Cheng Wei, Hui-Chen Hsu, Shu-Hau Feng, Wu-Shiung Feng
A 24GHz low-power CMOS receiver design. ISCAS (2008)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
Model-order reductions for MIMO systems using global Krylov subspace methods. Math. Comput. Simul. 79 (4) (2008)
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis. ISCAS (2007)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
Lyapunov-Based Error Estimations of MIMO Interconnect Reductions by Using the Global Arnoldi Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2007)
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
On the Equivalent of Structure Preserving Reductions Approach and Adjoint Networks Approach for VLSI Interconnect Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2007)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm. IEICE Trans. Electron. (6) (2006)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
The global Lanczos method for MIMO interconnect order reductions. ISCAS (2006)
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions. APCCAS (2006)
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
A Brief Comparison of Two-phase and NOR-based Four-phase Pipelined Asynchronous Systems. J. Inf. Sci. Eng. 22 (4) (2006)
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
Model-Order Reduction Algorithm with Structure Preserving Techniques. APCCAS (2006)
Chia-Chi Chu, Herng-Jer Lee, Ming-Hong Lai, Wu-Shiung Feng
An Adjoint Network Approach for RLCG Interconnect Model Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
XNOR-based double-edge-triggered flip-flop for two-phase pipelines. IEEE Trans. Circuits Syst. II Express Briefs (2) (2006)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
The Multiple Point Global Lanczos Method for Multiple-Inputs Multiple-Outputs Interconnect Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2006)
Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
MIMO interconnects order reductions by using the global Arnoldi algorithm. ISCAS (2006)
Herng-Jer Lee, Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
Moment Computations of Distributed Coupled RLC Interconnects with Applications to Estimating Crosstalk Noise. IEICE Trans. Electron. (6) (2005)
Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen, Wu-Shiung Feng
A 1.8 V, 0.3 mW, 10-bit SA-ADC with new self-timed timing control for biomedical applications. ISCAS (1) (2005)
Ming-Chang Sun, Ying-Haw Shu, Shing Tenqchen, Wu-Shiung Feng
A One-Step Input Matching Method for Cascode CMOS Low-Noise Amplifiers. IEICE Trans. Electron. (3) (2005)
Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng
Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2005)
Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng
Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai
Interconnect model reductions by using the AORA algorithm with considering the adjoint network. ISCAS (2) (2005)
Ying-Haw Shu, Shing Tenqchen, Ming-Chang Sun, Wu-Shiung Feng
An XNOR-based Double-edge-triggered Flip-Flop for Two-phase Pipelines. CCCT (1) (2004)
Shing Tenqchen, Ying-Haw Shu, Ming-Chang Sun, Wu-Shiung Feng
Blind Signal Extraction Algorithm for the License Plate Matching of Vehicle Positioning System. DELTA (2004)
Herng-Jer Lee, Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng
Applications of tree/link partitioning for moment computations of general lumped RLC networks with resistor loops. ISCAS (1) (2004)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Moment Computations of Nonuniform Distributed Coupled RLC Trees with Applications to Estimating Crosstalk Noise. ISQED (2004)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Generalizations of adjoint networks technique for RLC interconnects model-order reductions. ISCAS (1) (2004)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Moment Computations of Lumped Coupled RLC Trees with Applications to Estimating Crosstalk Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Interconnect modeling and sensitivity analysis using adjoint networks reduction technique. ISCAS (4) (2003)
Ming-Chang Sun, Shing Tenqchen, Ying-Haw Shu, Wu-Shiung Feng
A 2.4 GHz CMOS image-reject low noise amplifier. ISCAS (1) (2003)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Crosstalk estimation in high-speed VLSI interconnect using coupled RLC-tree models. APCCAS (1) (2002)
Chin Hsia, Ming-Hong Lai, Wu-Shiung Feng
On-board effective inductance measurement. APCCAS (1) (2002)
Shing Tenqchen, Ji-Horn Chang, Wu-Shiung Feng, Bor-Sheng Jeng
Pipelining Extended Givens Rotation RLS Adaptive Filters. DELTA (2002)
Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng
Intelligent multipoint Arnoldi (IMA) approximations of FIR filters by low-order linear-phase IIR filters. ISCAS (1) (2002)
Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage. ISCAS (4) (2001)
Cheng-Chung Hsu, Wu-Shiung Feng
Testable design of multiple-stage OTA-C filters. IEEE Trans. Instrum. Meas. 49 (5) (2000)
Lan-Da Van, Chih-Chun Tang, Shing Tenqchen, Wu-Shiung Feng
A new VLSI architecture without global broadcast for 2-D digital filters. ISCAS (2000)
Lan-Da Van, Shing Tenqchen, Chia-Hsun Chang, Wu-Shiung Feng
A tree-systolic array of DLMS adaptive filter. ICASSP (1999)
Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng
Design of a lower-error fixed-width multiplier for speech processing application. ISCAS (3) (1999)
Chun-Jung Chen, Wu-Shiung Feng
Relaxation-based transient sensitivity computations for MOSFET circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (2) (1995)
Jyh-Herng Wang, Jen-Teng Fan, Wu-Shiung Feng
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits. EDAC-ETC-EUROASIC (1994)
Jyh-Ming Wang, Sung-Chuan Fang, Wu-Shiung Feng
New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid State Circuits 29 (7) (1994)
Chung-Jung Chen, Wu-Shiung Feng
Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform Eelaxation. DAC (1994)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (8) (1992)
Sung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee
A New Efficient Approach to Multilayer Channel Routing Problem. DAC (1992)
Chun-Jung Chen, Jyuo-Min Shyu, Wu-Shiung Feng
Transient Sensitivity Computation for Waveform Relaxation Based Timing Simulation. ICCAD (1991)
Pei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng
A knowledge-based program for compacting mask layout of integrated circuits. Comput. Aided Des. 23 (3) (1991)
Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. DAC (1991)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22 (7) (1990)
Pei-Yung Hsiao, H. F. Steven Chen, Wu-Shiung Feng
A new control strategy for an artificial intelligence approach to VLSI layout compaction. Integr. 10 (1) (1990)
Pei-Yung Hsiao, Wu-Shiung Feng
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (5) (1990)
Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng
Tile-Expansion Router. J. Inf. Sci. Eng. 6 (3) (1990)
S. F. Steven Chen, Pei-Yung Hsiao, Wu-Shiung Feng, Shun-Nan Dai, Wen-Zyh Wang
The Control Model for a Knowledge-Based Approach to VLSI Compaction Design. IFIP Congress (1989)
Pei-Yung Hsiao, Chen Yung Syau, Wu-Shiung Feng, T. M. Parng, Cheng-Chung Hsu
A rule-based compactor for VLSI/CAD mask layout. COMPSAC (1988)