Login / Signup

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs.

Kuan-Yu LinHong-Ting LinTsung-Yi HoChia-Chun Tsai
Published in: ACM Trans. Design Autom. Electr. Syst. (2012)
Keyphrases
  • high speed
  • clock frequency
  • power consumption
  • tree structure
  • insertions and deletions
  • dynamic environments
  • r tree
  • low power
  • tree structures
  • buffer size
  • loss probability
  • duty cycle