Trong-Yen Lee

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 12

Top Topics

Convolutional Neural Network

Top Venues

Comput. Electr. Eng.

Publications

Jingmin Yang, Trong-Yen Lee, Wen-Ta Lee, Li Xu
Construction and Implementation of Wireless Network Online Learning System Based on Edge Computing. Int. J. Emerg. Technol. Learn. 17 (21) (2022)
Jingmin Yang, Trong-Yen Lee, Wen-Ta Lee, Li Xu
A Design and Application of Municipal Service Platform Based on Cloud-Edge Collaboration for Smart Cities. Sensors 22 (22) (2022)
Jingmin Yang, Trong-Yen Lee, Wenjie Zhang
Smart Cities in China: A Brief Overview. IT Prof. 23 (3) (2021)
Trong-Yen Lee, I-An Lin, Jui-Yuan Yu, Jing-min Yang, Yu-Chun Chang
High Efficiency Disease Detection for Potato Leaf with Convolutional Neural Network. SN Comput. Sci. 2 (4) (2021)
Trong-Yen Lee, Yen-Lin Chen, Yu-Cheng Fan
Next-Generation Electronics and Sensing Technology. Sensors 21 (23) (2021)
Trong-Yen Lee, I-An Lin, Ren-Hong Liao
Design of a FlexRay/Ethernet Gateway and Security Mechanism for In-Vehicle Networks. Sensors 20 (3) (2020)
Jingmin Yang, Trong-Yen Lee, Baoxing Chen, Wenjie Zhang
A Comprehensive Teaching Reform Model for a Computer Networks Course Based on Integrated Information Systems. iJET 14 (18) (2019)
Trong-Yen Lee, Po-Hsuan Hung, Ju-Tse Tsai, I-An Lin
Personalized ACC System for Smart Vehicles. ICCE-TW (2019)
Trong-Yen Lee, I-An Lin, Jun-Jie Wang, Ju-Tse Tsai
A Reliability Scheduling Algorithm for the Static Segment of FlexRay on Vehicle Networks. Sensors 18 (11) (2018)
Trong-Yen Lee, Chia-Wei Kuo, I-An Lin
High performance CAN/FlexRay gateway design for in-vehicle network. DSC (2017)
Trong-Yen Lee, Chi-Han Huang, Min-Jea Liu, Jhen-Syuan Chen
Adaptive instruction codec architecture design for network-on-chip. Comput. Electr. Eng. 51 (2016)
Trong-Yen Lee, Chi-Han Huang, Wei-Cheng Chen, Min-Jea Liu
A low-area dynamic reconfigurable MDC FFT processor design. Microprocess. Microsystems 42 (2016)
Trong-Yen Lee, Kuang-Hua Chang, Chi-Han Huang, Cheng-Hsiu Kang, Min-Jea Liu
Power-saving dynamic allocati on strategy for clouding server. ICCE-TW (2015)
Trong-Yen Lee, Chi-Han Huang, Bo-Hao Wang, Cheng-Hsiu Kang, Jen-Yao Chen, I-Hsin Chou
Energy-saving LED control module for agent-based Micro-Grid systems. ICCE-TW (2014)
Trong-Yen Lee, Chi-Han Huang
Design of Smart Power-Saving Architecture for Network on Chip. VLSI Design 2014 (2014)
Trong-Yen Lee, Wei-Cheng Chen, Chi-Han Huang
Design of Low-Complexity 4-Path Dynamic Reconfigurable MDC FFT Processor. ICS (2014)
Trong-Yen Lee, Nian-You Lin, Wei-Cheng Chen, Haixia Wu
An Efficient Task Placement Method for Reconfigurable FPGA Systems. CISIS (2013)
Trong-Yen Lee, Min-Jea Liu, Chia-Chen Fan, Chia-Chun Tsai, Haixia Wu
Low Complexity Digit-Serial Multiplier over GF(2^m) Using Karatsuba Technology. CISIS (2013)
Trong-Yen Lee, Chi-Feng Lee
Microcontroller based automatic parking system. ICMLC (2012)
Wen-Chieh Chen, Shih-Chia Huang, Trong-Yen Lee
An Efficient Reconfigurable Architecture Design and Implementation of Image Contrast Enhancement Algorithm. HPCC-ICESS (2012)
Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. Integr. 45 (1) (2012)
Chia-Chun Tsai, Tsung-Ming Liu, Trong-Yen Lee
Micro fuel cell power management circuit design for portable devices. FSKD (2012)
Chia-Chun Tsai, Sheng-Bin Dai, Trong-Yen Lee
The RF Circuit Design of Power and Data Contactless Transmission for ISO/IEC 14443-2 Type B. J. Circuits Syst. Comput. 20 (8) (2011)
Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2011)
Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. Integr. 44 (1) (2011)
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
Antenna Violation Avoidance/Fixing for X-clock routing. ISQED (2010)
Chia-Chun Tsai, Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee
Double-via insertion enhanced X-architecture clock routing for reliability. ISCAS (2010)
Trong-Yen Lee, Che-Cheng Hu, Li-Wen Lai, Chia-Chun Tsai
Hardware Context-Switch Methodology for Dynamically Partially Reconfigurable Systems. J. Inf. Sci. Eng. 26 (4) (2010)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion. Circuits Syst. Signal Process. 28 (6) (2009)
Chia-Chun Tsai, Kai-Wei Hong, Trong-Yen Lee
A Bisection-Based Power Reduction Design for CMOS Flash Analog-to-Digital converters. J. Circuits Syst. Comput. 18 (5) (2009)
Chia-Chun Tsai, Chin-Yen Lin, Yuh-Shyan Hwang, Trong-Yen Lee
The Design of a Li-ion Battery Charger Based on Multimode LDO Technology. J. Circuits Syst. Comput. 18 (5) (2009)
Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
X-clock routing based on pattern matching. SoCC (2008)
Chia-Chun Tsai, Wei-Shi Lin, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee
Layer assignment considering manufacturability in X-architecture clock tree. CIT (2008)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee
GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
An Efficiently Hardware-Software Partitioning for Embedded Multiprocessor FPGA Systems. IMECS (2007)
Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee
Zero-Skew Driven Buffered RLC Clock Tree Construction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2007)
Trong-Yen Lee, Yang-Hsin Fan, Yu-Min Cheng, Chia-Chun Tsai, Rong-Shue Hsiao
Enhancement of Hardware-Software Partition for Embedded Multiprocessor FPGA Systems. IIH-MSP (2007)
Chia-Chun Tsai, Huang-Chi Chou, Trong-Yen Lee, Rong-Shue Hsiao
A single chip image sensor embedded smooth spatial filter with A/D conversion. ISCAS (2006)
Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao
Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion. APCCAS (2006)
Chia-Chun Tsai, Hann-Cheng Huang, Trong-Yen Lee, Wen-Ta Lee, Jan-Ou Wu
Using Stack Reconstruction on RTL Orthogonal Scan Chain Design. J. Inf. Sci. Eng. 22 (6) (2006)
Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao
Coupling aware RLC-based clock routings for crosstalk minimization. ISCAS (2006)
Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee
Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction. APCCAS (2006)
Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai
Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion. ICICIC (2) (2006)
Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang
A new low-power turbo decoder using HDA-DHDD stopping iteration. ISCAS (2) (2005)
Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee
Zero-Skew Driven for RLC Clock Tree Construction in SoC. ICITA (1) (2005)
Yuh-Shyan Hwang, Lu-Po Liao, Chia-Chun Tsai, Wen-Ta Lee, Trong-Yen Lee, Jiann-Jong Chen
A new CCII-based pipelined analog to digital converter. ISCAS (6) (2005)
Pao-Ann Hsiung, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
SESAG: an object-oriented application framework for real-time systems. Softw. Pract. Exp. 35 (10) (2005)
Trong-Yen Lee, Yang-Hsin Fan, Tsung-Hsun Yang, Chia-Chun Tsai, Wen-Ta Lee, Yuh-Shyan Hwang
RCGES: Retargetable Code Generation for Embedded Systems. ATVA (2004)
Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jih-Ming Fu, Win-Bin See
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software. IEEE Trans. Software Eng. 30 (10) (2004)
Trong-Yen Lee, Pao-Ann Hsiung
Embedded software synthesis and prototyping. IEEE Trans. Consumer Electron. 50 (1) (2004)
Trong-Yen Lee, Pao-Ann Hsiung, I-Mu Wu, Feng-Shi Su
RESS: Real-Time Embedded Software Synthesis and Prototyping Methodology. RTCSA (2003)
Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
Software Platform for Embedded Software Development. RTCSA (2003)
Pao-Ann Hsiung, Cheng-Yi Lin, Trong-Yen Lee
Quasi-Dynamic Scheduling for the Synthesis of Real-Time Embedded Software with Local and Global Deadlines. RTCSA (2003)
Pao-Ann Hsiung, Trong-Yen Lee, Feng-Shi Su
Formal Synthesis and Code Generation of Real-Time Embedded Software using Time-Extended Quasi-Static Scheduling. APSEC (2002)
Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen
VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. Symposium on Object-Oriented Real-Time Distributed Computing (2002)
Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
TCN: Scalable Hierarchical Hypercubes. ICPADS (2002)
Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen
Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. APSEC (2001)
Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. PDPTA (1999)
Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. ACM Trans. Design Autom. Electr. Syst. 3 (2) (1998)
Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen
Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. TOOLS (24) (1997)