Wei-Bin Yang

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 10

Top Topics

Wavelet Transform

Top Venues

Comput. Electr. Eng.

Publications

Su-Xi Yu, Jing-Yuan He, Yi Wang, Yu-Jiao Cai, Jun Yang, Bo Lin, Wei-Bin Yang, Jian Ruan
Texture Classification Network Integrating Adaptive Wavelet Transform. CoRR (2024)
Rui-Yang Ju, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang
ThreshNet: An Efficient DenseNet using Threshold Mechanism to Reduce Connections. CoRR (2022)
Wei-Bin Yang, Kuo-Ning Chang, Lu-Chun Yeh
A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design. IEEE Syst. J. 16 (3) (2022)
Rui-Yang Ju, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang
ThreshNet: An Efficient DenseNet Using Threshold Mechanism to Reduce Connections. IEEE Access 10 (2022)
Wei-Bin Yang, Chi-Hsuan Sun, Diptendu Sinha Roy, Yi-Mei Chen
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input. IEEE Access 9 (2021)
Shun Shen Peter Wang, Yin-Tien Wang, Choung-Lii Chao, Wei-Bin Yang
Instrumentation of Twin-MCMs based mutual-test. Microelectron. J. 114 (2021)
Wei-Bin Yang, Shu-Yu Ku, Chun-Wei Wang, Li-Lun Chu
Asynchronous Domino Binary search Digital LDO. ISPACS (2021)
Wei-Bin Yang, Ming-Hao Hong, Jsung Mo Shen
A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator. J. Signal Process. Syst. 89 (2) (2017)
Wei-Bin Yang, Yu-Yao Lin, Yu-Lung Lo
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. Circuits Syst. Signal Process. 36 (12) (2017)
Wei-Bin Yang, Ming-Hao Hong
A 25 MHz crystal less clock generator with background calibration against process and temperature variation. Comput. Electr. Eng. 52 (2016)
Wei-Bin Yang, Yu-Yao Lin, Chi-Hsiung Wang, Kuo-Ning Chang, Cing-Huan Chen, Yu-Lung Lo
Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. ISPACS (2015)
Wei-Bin Yang, Chi-Hsiung Wang, Sheng-Shih Yeh, Chao-Cheng Liao
A multiple frequency clock generator using wide operation frequency range phase interpolator. Microelectron. J. 44 (8) (2013)
Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang
A GHz full-division-range programmable divider with output duty-cycle improved. DDECS (2013)
Wei-Bin Yang, Chi-Hsiung Wang, I-Ting Chuo, Huang-Hsuan Hsu
A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application. ISPACS (2012)
Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. Microelectron. J. 42 (1) (2011)
Wei-Bin Yang, Chang-Yo Hsieh
A synthesizable pseudo fractional-N clock generator with improved duty cycle output. Microelectron. J. 42 (10) (2011)
Zheng-Yi Huang, Jen-Shiun Chiang, Wei-Bin Yang, Chi-Hsiung Wang
A new temperature independent current controlled oscillator. ISPACS (2011)
Wei-Bin Yang, Yu-Lung Lo, Ting-Sheng Chao
Clock Generator with 50% Duty Cycle Output. IEICE Trans. Electron. (3) (2010)
Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs (5) (2009)
Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. (6) (2009)
Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS (2009)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS (2008)
Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS (2007)
Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ISCAS (2007)
Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS (2006)
Ting-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang
Analysis and Design of High Performance, Low Power Multiple Ports Register Files. APCCAS (2006)
Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. ICECS (2006)
Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang
The new improved pseudo fractional-N clock generator with 50% duty cycle. ISCAS (2006)
Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD (2005)
Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) (2005)
Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) (2004)
Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) (2001)
Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang
A difference detector PFD for low jitter PLL. ICECS (2001)
Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu
A CMOS low power voltage controlled oscillator with split-path controller. ICECS (2001)
Kuo-Hsing Cheng, Wei-Bin Yang
The suggestion for CFS CMOS buffer. ICECS (1999)