Chih-Hsien Chang

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 14

Top Topics

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. ISSCC (2022)
Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Yu-Tso Lin, Tsung-Hsien Tsai, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Tsung-Che Lu, Chin-Ming Fu, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Kenny Hsieh
A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications. VLSI Circuits (2021)
Chao-Chieh Li, Min-Shueh Yuan, Yu-Tso Lin, Chia-Chun Liao, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS. IEEE Trans. Circuits Syst. (12) (2020)
Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. IEEE J. Solid State Circuits 55 (4) (2020)
Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin L.-S. Loke, Mark Chen
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. VLSI Circuits (2020)
Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. VLSI Circuits (2019)
Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. VLSI Circuits (2018)
Chao-Chieh Li, Min-Shueh Yuan, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply. IEEE J. Solid State Circuits 53 (12) (2018)
Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. VLSI Circuits (2018)
Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. ISSCC (2018)
Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. ISSCC (2017)
Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen
, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. CICC (2017)
Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits (2016)
Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. ISSCC (2015)
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. IEEE J. Solid State Circuits 49 (4) (2014)
Chih-Hsien Chang, Ming Chuan Kuo, Jenn-Iuan Chen, Polun Chang
Did Prototyping Approach Really Help Us in Developing NIS? Nursing Informatics (2012)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique. IEEE J. Solid State Circuits 46 (5) (2011)
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC (2010)
Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS (2008)
Meei-Ling Jan, Keh-Shih Chuang, Guo-Wei Chen, Yu-Ching Ni, Sharon C. Chen, Chih-Hsien Chang, Jay Wu, Te-Wei Lee, Ying-Kai Fu
A three-dimensional registration method for automated fusion of micro PET-CT-SPECT whole-body images. IEEE Trans. Medical Imaging 24 (7) (2005)
Chang-Hua Lien, Chih-Hsien Chang, Chih-Chieh Liao, Kuo-Kuang Fan
Robust asymptotic stability of uncertain neutral systems via LMI and GAs. SMC (2003)