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14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.

Tsung-Hsien TsaiMin-Shueh YuanChih-Hsien ChangChia-Chun LiaoChao-Chieh LiRobert Bogdan Staszewski
Published in: ISSCC (2015)
Keyphrases
  • user friendly
  • phase locked loop
  • high speed
  • packet loss
  • video coding