A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Wei-Chih ChenChien-Chun TsaiChih-Hsien ChangYung-Chow PengFu-Lung HsuehTsung-Hsin YuJinn-Yeh ChienWen-Hung HuangChi-Chang LuMu-Shan LinChin-Ming FuShu-Chun YangChung-Wing WongWan-Te ChenChin-Hua WenLi Yueh WangChiang PuPublished in: CICC (2010)
Keyphrases
- cmos technology
- low power
- decision feedback
- high speed
- ultra wideband
- spl times
- low voltage
- power consumption
- parallel processing
- multi channel
- bit error rate
- wireless systems
- power dissipation
- low cost
- multipath
- silicon on insulator
- real time
- wireless channels
- image sensor
- communication systems
- ofdm system
- digital signal processing