Chi-Chang Lu

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 5

Top Topics

Individual Preferences

Top Venues

IET Circuits Devices Syst.

Publications

Chi-Chang Lu, Ding-Ke Huang
A 10-Bits 50-MS/s SAR ADC Based on Area-Efficient and Low-Energy Switching Scheme. IEEE Access 8 (2020)
Chang-Chi Lee, Hou-Ming Chen, Chi-Chang Lu, Bo-Yi Lee, Hsien-Chi Huang, He-Sheng Fu, Yong-Xin Lin
A High-Precision Bandgap Reference With a V-Curve Correction Circuit. IEEE Access 8 (2020)
Chi-Chang Lu, Ding-Ke Huang
1.2 V 10-bits 40 MS/s CMOS SAR ADC for low-power applications. IET Circuits Devices Syst. 13 (6) (2019)
Chi-Chang Lu, Sheng-Yan Lai
Capacitive digital-to-analog converter for low-power SAR ADCs. ICCE-TW (2019)
Chi-Chang Lu, Chung-Hsien Wu, Hui-Kai Su
Intelligent Infant Monitoring System Involving a Wi-Fi Wireless Sensor Network. IIH-MSP (2) (2018)
Chi-Chang Lu, Po-Hsien Lin
A Study of the Accessible Approach to Replace the Reservoir Silt Glaze with New Formula. HCI (12) (2015)
Chi-Chang Lu, Po-Hsien Lin
Cultural Creativity in Design Strategy: A Case Study of User's Preference of a Bird-Shaped Teapot. HCI (19) (2014)
Chi-Chang Lu, Po-Hsien Lin
Research on Symbol Expression for Eye Image in Product Design: The Usage of the Chinese Traditional "Yun Wen". HCI (20) (2013)
Chi-Chang Lu
A 1.2V 10-bit 5 MS/s CMOS cyclic ADC. ISCAS (2013)
Tsung-Sum Lee, Chi-Chang Lu
A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit. Circuits Syst. Signal Process. 30 (5) (2011)
Po-Hsien Lin, Chi-Chang Lu, Mo-Li Yeh
Design for Aesthetic Experience. HCI (15) (2011)
Chi-Chang Lu, Po-Hsien Lin
A Study of Producing Ceramic Glaze Utilizing Shihmen Reservoir Silt. HCI (15) (2011)
Wei-Chih Chen, Chien-Chun Tsai, Chih-Hsien Chang, Yung-Chow Peng, Fu-Lung Hsueh, Tsung-Hsin Yu, Jinn-Yeh Chien, Wen-Hung Huang, Chi-Chang Lu, Mu-Shan Lin, Chin-Ming Fu, Shu-Chun Yang, Chung-Wing Wong, Wan-Te Chen, Chin-Hua Wen, Li Yueh Wang, Chiang Pu
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology. CICC (2010)
Tsung-Sum Lee, Chi-Chang Lu
Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers. Circuits Syst. Signal Process. 29 (2) (2010)
Chi-Chang Lu, Wei-Xiang Tung
A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC. ISCAS (2010)
Chi-Chang Lu, Wei-Xiang Tung, Chien-Kuo Huang
A CMOS low-voltage fully differential sample-and-hold circuit. APCCAS (2008)
Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. ISCAS (2007)
Tsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan
A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit. SoCC (2007)
Chi-Chang Lu, Tsung-Sum Lee
A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter. IEEE Trans. Circuits Syst. II Express Briefs (8) (2007)
Tsung-Sum Lee, Chi-Chang Lu, Shen-Hau Yu, Jian-Ting Zhan
A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal. ISCAS (4) (2005)
Tsung-Sum Lee, Chi-Chang Lu
A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2005)
Tsung-Sum Lee, Chi-Chang Lu
A fully differential low-voltage CMOS high-speed track-and-hold circuit. ISCAS (1) (2003)
Tsung-Sum Lee, Chi-Chang Lu
A low-voltage fully differential CMOS high-speed track-and-hold circuit. APCCAS (1) (2002)