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A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal.
Tsung-Sum Lee
Chi-Chang Lu
Shen-Hau Yu
Jian-Ting Zhan
Published in:
ISCAS (4) (2005)
Keyphrases
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cmos technology
low power
low voltage
power consumption
high speed
low cost
low power consumption
power management
mixed signal
power dissipation
image sensor
delay insensitive
logic circuits
parallel processing
vlsi circuits
flip flops
gate array
single chip
power reduction
real time
ultra low power