A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.
Tsung-Hsien TsaiRuey-Bin SheenSheng-Yun HsuYa-Tin ChangChih-Hsien ChangRobert Bogdan StaszewskiPublished in: ISSCC (2022)