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A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.

Tsung-Hsien TsaiRuey-Bin SheenSheng-Yun HsuYa-Tin ChangChih-Hsien ChangRobert Bogdan Staszewski
Published in: ISSCC (2022)
Keyphrases
  • general purpose
  • real time
  • data sets
  • neural network
  • machine learning
  • database systems
  • data structure
  • high speed
  • face detection