, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Chao-Chieh LiTsung-Hsien TsaiMin-Shueh YuanChia-Chun LiaoChih-Hsien ChangTien-Chien HuangHsien-Yuan LiaoChung-Ting LuHung-Yi KuoKenny HsiehMark ChenAugusto Ronchini XimenesRobert Bogdan StaszewskiPublished in: VLSI Circuits (2016)
Keyphrases
- metal oxide semiconductor
- power consumption
- clock gating
- high speed
- circuit design
- cmos technology
- clock frequency
- cmos image sensor
- low cost
- dielectric constant
- integrated circuit
- low power
- power supply
- silicon on insulator
- feature selection
- packet loss
- frequency band
- fault diagnosis
- mixed signal
- phase locked loop
- fuzzy logic
- single chip
- low frequency
- nm technology
- analog to digital converter
- expert systems