Saman Adham

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 4

Top Topics

Write Operations

Integrating Multiple

Diagnostic Problem Solving

External Memory

Top Venues

IEEE J. Solid State Circuits

Publications

Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang
Write Endurance and Integrated Margin-Expansion Schemes. ISSCC (2024)
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. ISSCC (2024)
Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Mei-Chen Chuang, Rawan Naous, Chao-Kai Chuang, Takeshi Hashizume, Dar Sun, Chia-Fu Lee, Kerem Akarvardar, Saman Adham, Tan-Li Chou, Mahmut Ersin Sinangil, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang
Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. ISSCC (2022)
Shih-Lien Lu, Cheng-En Lee, Peter Noel, Saman Adham, Ted Wong, Jonathan Chang
A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering. VLSI-DAT (2019)
Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee
/3D ICs. VLSI-DAT (2014)
Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. IEEE J. Solid State Circuits 49 (4) (2014)
Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT (2014)
Saman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh
The importance of DFX, a foundry perspective. ITC (2014)
Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC (2013)
Benoit Nadeau-Dostie, Saman Adham, Russell Abbott
Improved Core Isolation and Access for Hierarchical Embedded Test. IEEE Des. Test Comput. 26 (1) (2009)
Saman Adham, Benoit Nadeau-Dostie
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. MTDT (2004)
Saman Adham, Dhamin Al-Khalili, Côme Rozon, Douglas Racz
Comprehensive defect analysis and testability of current-mode logic circuits. ISCAS (2000)
Côme Rozon, Dhamin Al-Khalili, Saman Adham, Douglas Racz
Comparing defect coverage for current-mode logic and CMOS VLSI cells. ICECS (2000)
Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham
Design For Testability Method for CML Digital Circuits. DATE (1999)
Yuejian Wu, Saman Adham
Scan-based BIST fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
José M. Miranda, Scott Davidson, Peter Dziel, Saman Adham, Steve Millman
Test Reuse at System Level. VTS (1998)
Dhamin Al-Khalili, Saman Adham, Côme Rozon, Moazzem Hossain, Douglas Racz
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits. DFT (1998)
Saman Adham, Sanjay Gupta
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. Asian Test Symposium (1996)
Yuejian Wu, Saman Adham
BIST Fault Diagnosis in Scan-Based VLSI Environments. ITC (1996)
Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham
A New Hardware Fault Insertion Scheme for System Diagnostics Verification. ITC (1995)
Harry Hulvershorn, Paul Soong, Saman Adham
Linking Diagnostic Software to Hardware Self Test in Telecom Systems. ITC (1995)