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Harry Chuang
Publication Activity (10 Years)
Years Active: 2018-2023
Publications (10 Years): 6
Top Topics
Recent Progress
Operating Point
Magnetic Field
Top Venues
VLSI Circuits
ISSCC
IEEE J. Solid State Circuits
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Publications
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Po-Hao Lee
,
Chia-Fu Lee
,
Yi-Chun Shih
,
Hon-Jarn Lin
,
Yen-An Chang
,
Cheng-Han Lu
,
Yu-Lin Chen
,
Chieh-Pu Lo
,
Chung-Chieh Chen
,
Cheng-Hsiung Kuo
,
Tan-Li Chou
,
Chia-Yu Wang
,
J. J. Wu
,
Roger Wang
,
Harry Chuang
,
Yih Wang
,
Yu-Der Chih
,
Tsung-Yung Jonathan Chang
A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.
ISSCC
(2023)
Chung-Cheng Chou
,
Zheng-Jun Lin
,
Chien-An Lai
,
Chin-I Su
,
Pei-Ling Tseng
,
Wei-Chi Chen
,
Wu-Chin Tsai
,
Wen-Ting Chu
,
Tong-Chern Ong
,
Harry Chuang
,
Yu-Der Chih
,
Tsung-Yung Jonathan Chang
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range.
VLSI Circuits
(2020)
Yu-Der Chih
,
Yi-Chun Shih
,
Chia-Fu Lee
,
Yen-An Chang
,
Po-Hao Lee
,
Hon-Jarn Lin
,
Yu-Lin Chen
,
Chieh-Pu Lo
,
Meng-Chun Shih
,
Kuei-Hung Shen
,
Harry Chuang
,
Tsung-Yung Jonathan Chang
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
ISSCC
(2020)
William J. Gallagher
,
Eric Chien
,
Tien-Wei Chiang
,
Jian-Cheng Huang
,
Meng-Chun Shih
,
C. Y. Wang
,
Christine Bair
,
George Lee
,
Yi-Chun Shih
,
Chia-Fu Lee
,
Roger Wang
,
Kuei-Hung Shen
,
J. J. Wu
,
Wayne Wang
,
Harry Chuang
Recent Progress and Next Directions for Embedded MRAM Technology.
VLSI Circuits
(2019)
Yi-Chun Shih
,
Chia-Fu Lee
,
Yen-An Chang
,
Po-Hao Lee
,
Hon-Jarn Lin
,
Yu-Lin Chen
,
Ku-Feng Lin
,
Ta-Ching Yeh
,
Hung-Chang Yu
,
Harry Chuang
,
Yu-Der Chih
,
Tsung-Yung Jonathan Chang
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits
54 (4) (2019)
Yi-Chun Shih
,
Chia-Fu Lee
,
Yen-An Chang
,
Po-Hao Lee
,
Hon-Jarn Lin
,
Yu-Lin Chen
,
Ku-Feng Lin
,
Ta-Ching Yeh
,
Hung-Chang Yu
,
Harry Chuang
,
Yu-Der Chih
,
Tsung-Yung Jonathan Chang
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
VLSI Circuits
(2018)