Vivek Chickermane

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 9

Top Topics

Data Compression

Dagstuhl Castle

Top Venues

Publications

Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test 41 (4) (2024)
Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
PPA Optimization of Test Points in Automotive Designs. ITC (2022)
Stefano Di Carlo, Peilin Song, Vivek Chickermane
Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium. IEEE Des. Test 37 (4) (2020)
Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ITC (2019)
Irith Pomeranz, Vivek Chickermane, Srikanth Venkataraman
Observation Point Placement for Improved Logic Diagnosis based on Large Sets of Candidate Faults. VTS (2019)
Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox
Advancing test compression to the physical dimension. ITC (2017)
Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen
At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic. ATS (2015)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers. IEEE Des. Test 32 (4) (2015)
Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW (2015)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
Efficient testing of hierarchical core-based SOCs. ITC (2014)
Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSI Design (2014)
Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane
Innovative practices session 1C: Existing/emerging low power techniques. VTS (2014)
Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC (2013)
Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
SmartScan - Hierarchical test compression for pin-limited low power designs. ITC (2013)
Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers. ETS (2013)
Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. ITC (2012)
Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel
Automation of 3D-DfT Insertion. Asian Test Symposium (2011)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC (2010)
Krishna Chakravadhanula, Vivek Chickermane
Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Des. Test Comput. 26 (3) (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
Capture power reduction using clock gating aware test generation. ITC (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
Test Generation for State Retention Logic. ATS (2008)
Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC (2008)
Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane
Low Power Reduced Pin Count Test Methodology. ATS (2007)
Brian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman
Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology. ATS (2006)
Sanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi
Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics Analysis. ATS (2006)
Anis Uzzaman, Brion L. Keller, Vivek Chickermane
A Scalable Architecture for On-Chip Compression: Options and Trade-Offs. ATS (2006)
Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman
Practical Aspects of Delay Testing for Nanometer Chips. Asian Test Symposium (2005)
Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. Asian Test Symposium (2005)
Vivek Chickermane, Brian Foutz, Brion L. Keller
Channel Masking Synthesis for Efficient On-Chip Test Compression. ITC (2004)
Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane
An Economic Analysis and ROI Model for Nanometer Test. ITC (2004)
Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre
A building block BIST methodology for SOC designs: a case study. ITC (2001)
Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane
System-on-Chip Testability Using LSSD Scan Structures. IEEE Des. Test Comput. 18 (3) (2001)
Vivek Chickermane, Scott Richter, Carl Barnhart
Integrating Logic BIST in VLSI Designs with Embedded Memories. VTS (2000)
Vivek Chickermane, Kamran Zarrineh
Addressing Early Design-For-Test Synthesis in a Production Environment. ITC (1997)
Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer
A Design For Test Perspective on I/O Management. ICCD (1996)
Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. 3 (2) (1995)
Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
An observability enhancement approach for improved testability and at-speed test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
Addressing design for testability at the architectural level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (7) (1994)
Jaushin Lee, Vivek Chickermane, Janak H. Patel
Impact of high level functional constraints on testability. VTS (1993)
Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC (1993)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
Design for Testability Using Architectural Descriptions. ITC (1992)
Sungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel
APT: An Area-Performance-Testability Driven Placement Algorithm. DAC (1992)
Vivek Chickermane, Jaushin Lee, Janak H. Patel
A comparative study of design for testability methods using high-level and gate-level descriptions. ICCAD (1992)
Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel
Probe point insertion for at-speed test. VTS (1992)
Ravi Nair, Vivek Chickermane, Ray Chamberlain
Restructuring VLSI layout representations for efficiency. EURO-DAC (1991)
Vivek Chickermane, Janak H. Patel
A Fault Oriented Partial Scan Design Approach. ICCAD (1991)
Vivek Chickermane, Janak H. Patel
An optimization based approach to the partial scan design problem. ITC (1990)