Krishna Chakravadhanula

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 5

Top Topics

Lossy Image Compression

Failure Diagnosis

Compression Ratio

Top Venues

Publications

Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
PPA Optimization of Test Points in Automotive Designs. ITC (2022)
Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications. ITC (2019)
Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula
Improving Diagnosis Resolution and Performance at High Compression Ratios. ITC (2018)
Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula
High throughput multiple device diagnosis system. ITC (2017)
Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox
Advancing test compression to the physical dimension. ITC (2017)
Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW (2015)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
Efficient testing of hierarchical core-based SOCs. ITC (2014)
Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSI Design (2014)
Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
SmartScan - Hierarchical test compression for pin-limited low power designs. ITC (2013)
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
Low cost at-speed testing using On-Product Clock Generation compatible with test compression. ITC (2010)
Krishna Chakravadhanula, Vivek Chickermane
Automating IEEE 1500 Core Test—An EDA Perspective. IEEE Des. Test Comput. 26 (3) (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang
Capture power reduction using clock gating aware test generation. ITC (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman
Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?. Asian Test Symposium (2009)
Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor
Test Generation for State Retention Logic. ATS (2008)
Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. ITC (2008)
Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane
Low Power Reduced Pin Count Test Methodology. ATS (2007)