Akhil Garg

Publication Activity (10 Years)

Years Active: 2006-2014
Publications (10 Years): 0

Top Topics

Computationally Expensive

Top Venues

Publications

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
Efficient testing of hierarchical core-based SOCs. ITC (2014)
Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
SmartScan - Hierarchical test compression for pin-limited low power designs. ITC (2013)
Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto
State of the art low capture power methodology. ITC (2011)
Prashant Dubey, Akhil Garg, Shashank Mahajan
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. J. Electron. Test. 26 (6) (2010)
Swapnil Bahl, Rajiv Sarkar, Akhil Garg
Low Power Test. ITC (2008)
Akhil Garg, Prashant Dubey
On Chip Jitter Measurement through a High Accuracy TDC. ISQED (2008)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
Built in Defect Prognosis for Embedded Memories. DDECS (2007)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
GALS Based Shared Test Architecture for Embedded Memories. ISCAS (2007)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI (2007)
Akhil Garg, Prashant Dubey
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost. SoCC (2006)
Akhil Garg, Prashant Dubey
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT (2006)