Prashant Dubey

Publication Activity (10 Years)

Years Active: 2006-2017
Publications (10 Years): 1

Top Topics

Power Reduction

Cmos Technology

Optimization Strategies

Parallel Processing

Top Venues

Publications

Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen
A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision. ISCAS (2017)
Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. VLSI Design (2014)
Prashant Dubey, Rashmi Agarwal
38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS. VLSI Design (2013)
Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha
PODIA: Power Optimization through Differential Imbalanced Amplifier. VLSI Design (2013)
Prashant Dubey, Akhil Garg, Shashank Mahajan
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. J. Electron. Test. 26 (6) (2010)
Akhil Garg, Prashant Dubey
On Chip Jitter Measurement through a High Accuracy TDC. ISQED (2008)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
Built in Defect Prognosis for Embedded Memories. DDECS (2007)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
GALS Based Shared Test Architecture for Embedded Memories. ISCAS (2007)
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. ISVLSI (2007)
Akhil Garg, Prashant Dubey
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost. SoCC (2006)
Akhil Garg, Prashant Dubey
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. DFT (2006)