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Vaibhav Verma
ORCID
Publication Activity (10 Years)
Years Active: 2014-2023
Publications (10 Years): 10
Top Topics
Cmos Technology
Spl Times
Memory Usage
Design Space Exploration
Top Venues
MICRO
ISQED
WF-IoT
IEEE Comput. Archit. Lett.
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Publications
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Yimin Gao
,
Sergiu Mosanu
,
Mohammad Nazmus Sakib
,
Vaibhav Verma
,
Xinfei Guo
,
Mircea Stan
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores.
SOCC
(2023)
Xiaotian Zhao
,
Yimin Gao
,
Vaibhav Verma
,
Ruge Xu
,
Mircea Stan
,
Xinfei Guo
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units.
ACM Great Lakes Symposium on VLSI
(2023)
Vaibhav Verma
,
Tommy Tracy II
,
Mircea R. Stan
EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT.
Sustain. Comput. Informatics Syst.
35 (2022)
Mohammad Nazmus Sakib
,
Rahul Sreekumar
,
Vaibhav Verma
,
Tommy Tracy II
,
Mircea R. Stan
ATCPiM: Analog to Time Coded Processing in Memory for IoT at the Edge.
WF-IoT
(2021)
Vaibhav Verma
,
Fiza Akhtar
,
Anuj Grover
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology.
VDAT
(2020)
Elaheh Sadredini
,
Reza Rahimi
,
Vaibhav Verma
,
Mircea Stan
,
Kevin Skadron
eAP: A Scalable and Efficient In-Memory Accelerator for Automata Processing.
MICRO
(2019)
Elaheh Sadredini
,
Reza Rahimi
,
Vaibhav Verma
,
Mircea Stan
,
Kevin Skadron
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing.
IEEE Comput. Archit. Lett.
18 (2) (2019)
Yunfei Gu
,
Dengxue Yan
,
Vaibhav Verma
,
Mircea R. Stan
,
Xuan Zhang
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors.
DAC
(2018)
Xinfei Guo
,
Vaibhav Verma
,
Patricia Gonzalez-Guerrero
,
Mircea R. Stan
When "things" get older: Exploring circuit aging in IoT applications.
ISQED
(2018)
Xinfei Guo
,
Vaibhav Verma
,
Patricia Gonzalez-Guerrero
,
Sergiu Mosanu
,
Mircea R. Stan
Back to the Future: Digital Circuit Design in the FinFET Era.
J. Low Power Electron.
13 (3) (2017)
Vaibhav Verma
,
Sachin Taneja
,
Pritender Singh
,
Sanjeev Kumar Jain
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology.
SoCC
(2015)
Prashant Dubey
,
Gaurav Ahuja
,
Vaibhav Verma
,
Sanjay Kumar Yadav
,
Amit Khanuja
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.
VLSI Design
(2014)