38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS.
Prashant DubeyRashmi AgarwalPublished in: VLSI Design (2013)
Keyphrases
- power consumption
- nm technology
- cmos technology
- power management
- low power
- clock gating
- power dissipation
- silicon on insulator
- high speed
- clock frequency
- wide range
- software architecture
- analog vlsi
- power reduction
- low cost
- management system
- single chip
- parallel processing
- low voltage
- design considerations
- power supply
- multithreading
- power distribution