Login / Signup
SmartScan - Hierarchical test compression for pin-limited low power designs.
Krishna Chakravadhanula
Vivek Chickermane
Don Pearl
Akhil Garg
R. Khurana
Subhasish Mukherjee
P. Nagaraj
Published in:
ITC (2013)
Keyphrases
</>
low power
power consumption
high speed
low cost
single chip
high power
nm technology
vlsi architecture
gate array
vlsi circuits
wireless transmission
low power consumption
logic circuits
cmos technology
image compression
compression ratio
signal processor
power reduction
delay insensitive
image sensor
general purpose