Low Power Reduced Pin Count Test Methodology.

Krishna Chakravadhanula Nitin Parimi Brian Foutz Bing Li Vivek Chickermane

Published in: ATS (2007)

Keyphrases

low power
power consumption
low cost
high speed
high power
single chip
wireless transmission
vlsi circuits
logic circuits
vlsi architecture
digital signal processing
power reduction
cmos technology
power dissipation
image sensor
real time
delay insensitive
nm technology
gate array