Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.
Hiroyuki NakamuraAkio ShirokaneYoshihito NishizakiAnis UzzamanVivek ChickermaneBrion L. KellerTsutomu UbeYoshihiko TerauchiPublished in: Asian Test Symposium (2005)
Keyphrases
- low cost
- test cases
- low power
- power dissipation
- test data
- test generation
- software testing
- single chip
- circuit design
- test sequences
- real time
- regression testing
- testing process
- statistical tests
- test suite
- digital camera
- low power consumption
- image compression
- code coverage
- test case generation
- neural network
- hardware and software
- embedded systems
- image quality
- multiresolution
- test driven development
- data compression
- compression ratio
- energy consumption
- test data generation
- software development
- integration testing
- model based testing