Kamran Zarrineh

Publication Activity (10 Years)

Years Active: 1996-2011
Publications (10 Years): 0

Publications

Salvatore Pontarelli, Marco Ottavi, Adelio Salsano, Kamran Zarrineh
Feedback based droop mitigation. DATE (2011)
Kamran Zarrineh
Design for Test Challenges of High Performance/Low Power Microprocessors. DFT (2008)
Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara
Design and analysis of multiple weight linear compactors of responses containing unknown values. ITC (2005)
Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. ITC (2003)
Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
Automatic generation and compaction of March tests for memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane
System-on-Chip Testability Using LSSD Scan Structures. IEEE Des. Test Comput. 18 (3) (2001)
Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD (2001)
Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams
Defect Analysis and a New Fault Model for Multi-port SRAMs. DFT (2001)
Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor
Self test architecture for testing complex memory structures. ITC (2000)
Kamran Zarrineh, R. Dean Adams, Aneesha P. Deo
Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. MTDT (2000)
Kamran Zarrineh, Shambhu J. Upadhyaya
A New Framework For Automatic Generation, Insertion and Verification of Memory Built-In Self Test Units. VTS (1999)
Kamran Zarrineh, Shambhu J. Upadhyaya
Programmable Memory BIST and a New Synthesis Framework. FTCS (1999)
Kamran Zarrineh, Shambhu J. Upadhyaya
On Programmable Memory Built-In Self Test Architectures. DATE (1999)
Kamran Zarrineh, Shambhu J. Upadhyaya
A design for test perspective on memory synthesis. ISCAS (1) (1999)
Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty
A new framework for generating optimal March tests for memory arrays. ITC (1998)
Kamran Zarrineh, Shambhu J. Upadhyaya, Philip Shephard III
Automatic Insertion of Scan Structures to Enhance Testability of Embedded Memories, Cores and Chips. VTS (1998)
Vivek Chickermane, Kamran Zarrineh
Addressing Early Design-For-Test Synthesis in a Production Environment. ITC (1997)
Kamran Zarrineh, Vivek Chickermane, Gareth Nicholls, Mike Palmer
A Design For Test Perspective on I/O Management. ICCD (1996)