Ramesh C. Tekumalla

Publication Activity (10 Years)

Years Active: 1996-2018
Publications (10 Years): 2

Top Topics

Issues And Trends

Vlsi Architecture

Top Venues

Publications

M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla
Innovative practices on memory test practice. VTS (2018)
Ramesh C. Tekumalla
Clock Domain Imbalances and Their Impact on Test Architecture. NATW (2015)
Surbhi Bansal, Aviansh Mendhalkar, Ramesh C. Tekumalla
On Handling Memory Scan Chains. NATW (2014)
Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane
Innovative practices session 1C: Existing/emerging low power techniques. VTS (2014)
Ramesh C. Tekumalla, Prakash Krishnamoorthy
On-chip Clock Testing and Frequency Measurement. NATW (2014)
Ramesh C. Tekumalla, Prakash Krishnamoorthy
Local Repair Signature Handling for Repairable Memories. NATW (2014)
Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene
Innovative practices session 2C: Memory test. VTS (2013)
Prakash Krishnamoorthy, Ramesh C. Tekumalla
Quotient prediction for low power division. SoCC (2013)
Prakash Krishnamoorthy, Ramesh C. Tekumalla
Power aware transformation of bandlimited signals. SoCC (2013)
Ramesh C. Tekumalla
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. VLSI Design (2006)
Ramesh C. Tekumalla
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. ITC (2003)
Ramesh C. Tekumalla, Scott Davidson
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. ITC (2002)
Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar
On Diagnosing Path Delay Faults in an At-Speed Environment. VTS (2001)
Ramesh C. Tekumalla, Premachandran R. Menon
Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (12) (2001)
Ramesh C. Tekumalla
On Test Set Generation for Efficient Path Delay Fault Diagnosis. VTS (2000)
Ramesh C. Tekumalla, Premachandran R. Menon
On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 49 (3) (2000)
Ramesh C. Tekumalla, Premachandran R. Menon
Robust testability of primitive faults using test points. ITC (1999)
Ramesh C. Tekumalla, Premachandran R. Menon
On primitive fault test generation in non-scan sequential circuits. ICCAD (1998)
Ramesh C. Tekumalla, Premachandran R. Menon
Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Test generation for primitive path delay faults in combinational circuits. ICCAD (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design (1996)