Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.

Ramesh C. Tekumalla Premachandran R. Menon

Published in: ICCD (1997)

Keyphrases

analog circuits
logic synthesis
power dissipation
high speed
sufficient conditions
genetic algorithm
circuit design
program synthesis
scan data
functional programs
real time
case study
critical path
sequential search
delay insensitive