Premachandran R. Menon

Publication Activity (10 Years)

Years Active: 1968-2006
Publications (10 Years): 0

Publications

Premachandran R. Menon, Weifeng Xu, Russell Tessier
Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Ramesh C. Tekumalla, Premachandran R. Menon
Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (12) (2001)
Ian G. Harris, Premachandran R. Menon, Russell Tessier
BIST-based delay path testing in FPGA architectures. ITC (2001)
Ramesh C. Tekumalla, Premachandran R. Menon
On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 49 (3) (2000)
Ramesh C. Tekumalla, Premachandran R. Menon
Robust testability of primitive faults using test points. ITC (1999)
Ramesh C. Tekumalla, Premachandran R. Menon
On primitive fault test generation in non-scan sequential circuits. ICCAD (1998)
Ramesh C. Tekumalla, Premachandran R. Menon
Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Test generation for primitive path delay faults in combinational circuits. ICCAD (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD (1997)
Ramesh C. Tekumalla, Premachandran R. Menon
Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design (1996)
Wuudiann Ke, Premachandran R. Menon
Multifault testability of delay-testable circuits. VTS (1995)
Wuudiann Ke, Premachandran R. Menon
Synthesis of Delay-Verifiable Combinational Circuits. IEEE Trans. Computers 44 (2) (1995)
Wuudiann Ke, Premachandran R. Menon
Multifault and delay-fault testability of multilevel circuits. J. Electron. Test. 6 (3) (1995)
Wuudiann Ke, Premachandran R. Menon
Path-delay-fault testable nonscan sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (5) (1995)
Wuudiann Ke, Premachandran R. Menon
Delay-testable implementations of symmetric functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Wuudiann Ke, Premachandran R. Menon
Delay-Verifiability of Combinational Circuits Based on Primitive Faults. ICCD (1994)
Wuudiann Ke, Premachandran R. Menon
Synthesis of Delay-Verifiable Two-Level Circuits. EDAC-ETC-EUROASIC (1994)
Hitesh Ajuha, Premachandran R. Menon
Delay Reduction by Segment Substitution. EDAC-ETC-EUROASIC (1994)
Wuudiann Ke, Premachandran R. Menon
Realization of fully path-delay-fault testable non-scan sequential circuits. VTS (1994)
Ohyoung Song, Premachandran R. Menon
3-valued trace-based fault simulation of synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Ohyoung Song, Premachandran R. Menon
Acceleration of trace-based fault simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (6) (1991)
Bong-Hee Park, Premachandran R. Menon
Robustly Scan-Testable CMOS Sequential Circuits. ITC (1991)
Bong-Hee Park, Premachandran R. Menon
Design of scan-testable CMOS sequential circuits. ITC (1990)
Ohyoung Song, Premachandran R. Menon
Parallel pattern fault simulation based on stem faults in combinational circuits. ITC (1990)
P. N. Anirudhan, Premachandran R. Menon
Symbolic Test Generation for Hierarchically Modeled Digital Systems. ITC (1989)
C. H. Chen, Premachandran R. Menon
An Approach to Functional Level Testability Analysis. ITC (1989)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
SMART and FAST: Test Generation for VLSI Scan-Design Circuits. IEEE Des. Test 3 (4) (1986)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
Test Generation In Lamp2: Concepts and Algorithms. ITC (1985)
Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller
Test Generation In Lamp2: System Overview. ITC (1985)
Gordon K. Lin, Premachandran R. Menon
Totally Preset Checking Experiments for Sequential Machines. IEEE Trans. Computers 32 (2) (1983)
Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon
A Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 (2) (1983)
Miron Abramovici, Premachandran R. Menon
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. ITC (1983)
Ytzhak H. Levendel, Premachandran R. Menon
Test Generation Algorithms for Computer Hardware Description Languages. IEEE Trans. Computers 31 (7) (1982)
Premachandran R. Menon, Stephen G. Chappell
Deductive Fault Simulation with Functional Blocks. IEEE Trans. Computers 27 (8) (1978)
Arthur D. Friedman, Premachandran R. Menon
Restricted Checking Sequences for Sequential Machines. IEEE Trans. Computers 22 (4) (1973)
Premachandran R. Menon, Arthur D. Friedman
Fault Detection in Iterative Logic Arrays. IEEE Trans. Computers 20 (5) (1971)
Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon
Design of Asynchronous Circuits Assuming Unbounded Gate Delays. IEEE Trans. Computers 18 (12) (1969)
Premachandran R. Menon
On Sequential Machine Decompositions for Reducing the Number of Delay Elements Inf. Control. 15 (3) (1969)
Chung-Jen Tan, Premachandran R. Menon, Arthur D. Friedman
Structural Simplification and Decomposition of Asynchronous Sequential Circuits. IEEE Trans. Computers 18 (9) (1969)
Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon
Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements. IEEE Trans. Computers 17 (2) (1968)