Synthesis of Delay-Verifiable Two-Level Circuits.

Wuudiann Ke Premachandran R. Menon

Published in: EDAC-ETC-EUROASIC (1994)

Keyphrases

analog circuits
logic synthesis
power dissipation
circuit design
power consumption
texture synthesis
critical path
quantum computing
delay insensitive
information systems
multi valued
high level synthesis
real time
vlsi circuits
analog vlsi
power reduction
low power
shortest path
real world
neural network