Identifying Redundant Path Delay Faults in Sequential Circuits.
Ramesh C. TekumallaPremachandran R. MenonPublished in: VLSI Design (1996)
Keyphrases
- built in self test
- power dissipation
- fault detection
- fault diagnosis
- multiple faults
- high speed
- path length
- delay insensitive
- fault detection and diagnosis
- critical path
- real time
- digital circuits
- optimal path
- sequential data
- routing protocol
- fault model
- test cases
- analog vlsi
- low cost
- highly redundant
- genetic algorithm