Path-delay-fault testable nonscan sequential circuits.

Wuudiann Ke Premachandran R. Menon

Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1995)

Keyphrases

power dissipation
fault detection
fault diagnosis
fault models
destination node
path length
high speed
analog vlsi
shortest path
transmission line
multiple faults
tunnel diode
data sets
fault model
path selection
critical path
low power
neural network