BIST-based delay path testing in FPGA architectures.
Ian G. HarrisPremachandran R. MenonRussell TessierPublished in: ITC (2001)
Keyphrases
- hardware implementation
- path length
- test cases
- high speed
- real time
- low cost
- neural network
- field programmable gate array
- software testing
- test data
- test set
- signal processing
- genetic algorithm
- shortest path
- test suite
- software engineering
- image processing
- software implementation
- multicast tree
- destination node
- parallel hardware
- fpga hardware