Stephan Eggersglüß

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 21

Top Venues

University of Bremen (PHD)

Education History

University of Bremen

PHD

Publications

Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test 41 (4) (2024)
Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 31 (4) (2023)
Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
On Reduction of Deterministic Test Pattern Sets. ITC (2021)
Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. LATS (2019)
Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena Ioana Vatajelu
IEEE European Test Symposium (ETS). ITC (2019)
Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Machine Learning-based Prediction of Test Power. ETS (2019)
Stephan Eggersglüß
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC (2019)
Stephan Eggersglüß
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC-Asia (2019)
Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS (2018)
Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Approximation-aware testing for approximate circuits. ASP-DAC (2018)
Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Machine learning based test pattern analysis for localizing critical power activity areas. DFT (2017)
Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE (2017)
Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken
Foreword. ETS (2017)
Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI (2017)
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Reconfigurable TAP controllers with embedded compression for large test data volume. DFT (2017)
Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. ATS (2017)
Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS (2016)
Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
SAT-based post-processing for regional capture power reduction in at-speed scan test generation. ETS (2016)
Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Exploring superior structural materials using multi-objective optimization and formal techniques. ISED (2016)
Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS (2016)
Stephan Eggersglüß
Compact test set generation for test compression-based designs. ETS (2015)
Stephan Eggersglüß, Rolf Drechsler
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. it Inf. Technol. 56 (4) (2014)
Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Automated formal verification of X propagation with respect to testability issues. IDT (2014)
Stephan Eggersglüß
Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. J. Electron. Test. 30 (5) (2014)
Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS (2014)
Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Optimization-based multiple target test generation for highly compacted test sets. ETS (2014)
Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Improved SAT-based ATPG: more constraints, better compaction. ICCAD (2013)
Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille
PASSAT 2.0: A multi-functional SAT-based testing framework. LATW (2013)
Stephan Eggersglüß
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill. Asian Test Symposium (2013)
Stephan Eggersglüß, Rolf Drechsler
A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Des. Test Comput. 29 (4) (2012)
Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
A new SAT-based ATPG for generating highly compacted test sets. DDECS (2012)
Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. Asian Test Symposium (2012)
Stephan Eggersglüß, Rolf Drechsler
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Stephan Eggersglüß, Rolf Drechsler
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE (2011)
Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS (2010)
Stephan Eggersglüß
Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen. Ausgezeichnete Informatikdissertationen (2010)
Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26 (3) (2010)
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS (2010)
Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Stephan Eggersglüß, Rolf Drechsler
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ETS (2009)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51 (2) (2009)
Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Timing Arc based logic analysis for false noise reduction. ICCAD (2009)
Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium (2009)
Stephan Eggersglüß, Rolf Drechsler
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL (2008)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation (2008)
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (7) (2008)
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL (2007)
Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV (2007)
Stephan Eggersglüß, Rolf Drechsler
Improving Test Pattern Compactness in SAT-based ATPG. ATS (2007)
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE (2007)
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
SWORD: A SAT like prover using word level information. VLSI-SoC (2007)
Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) (2007)
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS (2007)

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Publication Activity (10 Years)

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Stephan Eggersglüß